Modern integrated circuits are typically fabricated in multiple layers on a semiconductor (e.g. Silicon) wafer. During fabrication of an integrated circuit die, lithographic processes are widely used to lay down successive circuit layers that together define electronic devices on the integrated circuit die. During the fabrication process, a different mask is used to pattern each layer. Misalignment between successive layers of the integrated circuit die, which is caused by misalignment between the masks that define the various device layers, is present in substantially all integrated circuit dies to some degree. There is, however, a tolerable amount of misalignment that may exist in any given integrated circuit die before operation of the integrated circuit die is jeopardized.
In semiconductor manufacturing, the overlay between lithographically defined layers becomes more critical as lateral dimensions shrink in current and future technology nodes. In the 65 nm CMOS technology node, for example, poly-to-contact (poly stands for poly-Silicon which is the gate material) overlay becomes one of the most critical parameters for yield.
Referring to FIG. 1 of the drawings, there is provided a schematic cross-sectional view of a portion of an integrated circuit die configuration which is particularly sensitive to poly-to-contact short circuits due to misalignment of the respective layers of the integrated circuit die. The structure comprises a semiconductor substrate 100 typically of mono-crystalline Silicon, in which at least one isolation means 101, such as “shallow trench isolation” or STI, is formed to electrically separate, for example, n-type regions (not shown) and p-type regions (not shown) in a CMOS device, such regions being formed in the substrate 100 by, for example, conventional dopant diffusion or implantation. An active device 102 in the form of, for example, an NMOS or PMOS transistor is provided on the substrate 100, which device comprises a gate electrode structure 103 (formed by, for example, a conventional gate and spacer etching process) with a layer of poly-Silicon gate material 104. Conventional Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs) utilize poly-Silicon for forming gate electrodes, in view of its good thermal stability. In addition, poly-Silicon-based materials advantageously block implantation of dopant ions into the underlying channel region of the transistor, thereby facilitating the formation of self-aligned source and drain regions after gate electrode deposition/patterning is completed.
An integrated circuit is typically fabricated by etching trenches in a semiconductor substrate, in patterns defined by a photo-mask, then filling these trenches by an isolating material to realize electrically isolated active areas. Ion implantation is used to dope these areas as n-type or p-type. The active areas are then oxidized, after which step a gate material is deposited. A subsequent photolithography and anisotropic etching step is used to selectively remove gate material in order to construct, amongst other devices, field-effect transistors. Masked ion implantation steps are performed to highly dope the gate patterns and those active areas which are not covered by gate patterns, after which the formed transistors as well as other active and passive devices are interconnected as required, through respective contacts, by interconnection lines. Accordingly, in the structure illustrated in FIG. 1 of the drawings, the active device 102 is connected to the metal interconnecting line 105 by means of a contact 106 extending from the surface of the substrate 100.
In the exemplary structure shown, there is a critical distance d between the gate material 104 and the contact 106. Since the gate material and contact regions are patterned in separate lithographic steps, poly-to-contact shorts can be caused by misalignment between the respective patterns (which causes the distance between the gate material 104 and the contact 106 to be less than the critical distance), in addition to variation of the lateral dimensions of the gate 104 and contact 106.
For the 65 nm technology node, the minimal design rule for poly-to-contact distance d is very close to the accuracy capability of conventional lithographic tools and it is therefore imperative to have an adequate quantification of the distance between poly and respective contacts (and/or other critical electrical distances, such as, via-to-metal) in order to properly control the process and have a good diagnosis capability if an issue should arise. This quantification should ideally be possible in an early stage of the fabrication process (parametric test) and have acceptable process overheads in terms of measurement cost and time.
In one known method, during process development, a set of parametric test structures is used in which the poly-to-contact distance is systematically varied. The resultant test structures are placed on development reticules, which have a large fraction of their surface dedicated to engineering purposes, and measurements are performed on an individual basis in respect of the test structures to create a set of parametric test data defining the acceptable margin of variation in the critical distance. This is an expensive approach in terms of time and Silicon area, and as a result tends not to be used in production.
Other known methods describe the combination of poly-contact distance variations in a single “vernier” test structure combined with a digital test. It will be appreciated by a person skilled in the art that a vernier test structure is based on a well-known precision measurement method using interference patterns. In this approach, a large number of measurements, performed on digital remain measurement equipment, is necessary to determine the actual overlay margin; however, due to the requirement for digital measurement equipment, which is incompatible with parametric test equipment, such structures also are not generally used in production.
U.S. Pat. No. 6,221,681 relates to on-chip misalignment indication using misalignment circuit indicators fabricated in layers of an integrated circuit die wherein a current between two contacts varies as resistance between the contacts varies as a function of misalignment. Experimentation with varying degrees of misalignment results in a determination of a maximum and minimum amount of current between the contacts at a given voltage. The maximum and minimum amounts of current correspond to maximum misalignments in one and the other directions along the coordinate axis. Thus, the maximum and minimum amounts of current define an acceptable range of misalignment between successive layers. If the amount of current between the two contacts is either greater than the maximum amount of current or less than the minimum amount of current for a given voltage applied between the two contacts, misalignment between successive layers is considered to be out of tolerance, and the integrated circuit die is considered to have failed misalignment testing. In the described arrangement, there is provided a plurality of on-chip misalignment circuit indicators, each comprising a first conductor connecting a first contact region to a first pad and a second conductor connecting a second contact region to a second pad. The on-chip misalignment indicators may comprise any type of appropriate semiconductor device in which the current path through the device varies dependent upon the length, and hence the resistance, between locations in the device. Current measurements need to be performed in respect of each on-chip misalignment indicator, and at least one but more preferably a set of misalignment indicators are provided to detect misalignment along each respective coordinate axis of the integrated circuit die.
However, in addition to the fact that the arrangement described in U.S. Pat. No. 6,221,681 is concerned with the occurrence of unintentionally high resistance between layers of the device which are intended to be contacted, it is focused on separately tested test structures, i.e. it works with multiple measurements, one for each overlay variant, which is costly, particularly in terms of time.